Keysight Applied sciences introduced a collaboration with Intel Foundry to help Embedded Multi-die Interconnect Bridge-T (EMIB-T) know-how, a cutting-edge innovation geared toward bettering high-performance packaging options for synthetic intelligence (AI) and knowledge middle markets along with the help of Intel 18A course of node.
The calls for of AI and knowledge middle workloads proceed to develop in complexity, making certain dependable communication between chiplets and 3DICs is turning into more and more important. Excessive-speed knowledge switch and environment friendly energy supply are important to satisfy the efficiency calls for of next-generation semiconductor purposes. The semiconductor business addresses these challenges via rising open requirements, similar to Common Chiplet Interconnect Categorical™ (UCIe™) and Bunch of Wires (BoW). These requirements outline interconnect protocols for chiplets and 3DICs inside superior 2.5D/3D or laminate/natural packages, enabling constant, high-quality integration throughout completely different design platforms.
By adopting these requirements and verifying chiplets for compliance and hyperlink margin, Keysight EDA and Intel Foundry contribute to a rising chiplet interoperability ecosystem. The collaboration goals to scale back improvement prices, mitigate danger, and speed up innovation in semiconductor design.
Keysight EDA’s Chiplet PHY Designer, the most recent answer for high-speed digital chiplet design tailor-made to AI and knowledge middle purposes, now affords superior simulation capabilities for the UCIe™ 2.0 customary and introduces help for the Open Pc Undertaking BoW customary. As a complicated, system-level chiplet design and die-to-die (D2D) design answer, Chiplet PHY Designer permits pre-silicon stage validation, streamlining the trail to tapeout.
Suk Lee, VP & GM of Ecosystem Expertise Workplace, Intel Foundry
Our collaboration with Keysight EDA on EMIB-T silicon bridge know-how is a pivotal step in advancing high-performance packaging options. By integrating requirements like UCIe™ 2.0, we improve chiplet design flexibility for AI and knowledge middle purposes, accelerating innovation and making certain our prospects meet next-generation calls for with precision.
Niels Faché, Vice President and Common Supervisor, Keysight’s Design Engineering Software program
Keysight EDA’s pioneering Chiplet PHY Designer continues to redefine pre-silicon validation, empowering chiplet designers with fast, correct verification. By proactively embracing evolving requirements like UCIe™ 2.0 and BoW, and now with important help for Intel Foundry’s EMIB-T, we’re enabling engineers to speed up innovation and remove pricey design iterations earlier than manufacturing.
